The present invention relates to a circuit for selectively delaying an input trigger signal and more particularly to a delay circuit wherein precise increments of delay are selected in response to a control signal.
A delay circuit is a circuit having an output which is delayed by a prescribed time interval from an applied input. In a variable delay circuit, the time delay between the input signal and the output signal is adjustable, within limits, by the variation of one or more circuit parameters. In general, the variation in time delay is accomplished by the variation in the magnitude of a resistance, a capacitance, or a voltage.